1. Field of the Invention
This invention relates generally to semiconductor devices and, more particularly, to a semiconductor device having sidewall spacers and method of manufacturing thereof.
2. Description of the Related Art
SAC (self-aligned contact) technology has been utilized to form self-aligned contact holes between closely spaced gate stacks to accommodate ever-increasing density in ULSI (ultra large scale integration) circuits.
The SAC technology uses a selective etching process to form contact holes. In this technology, as shown in FIG. 1, a capping layer 10 and a pre-metal dielectric (PMD) layer 12 are deposited over a gate electrode 14, thereby forming closely-spaced gate stacks 16. Nitride sidewall spacers 15 are typically formed along opposite sides of the gate stacks 16. The selective etch process is designed to remove material from the PMD layer 12 faster than it removes material from the capping layer 10 or the sidewall spacers 15. Nitrides and oxides are typically used for the capping and PMD layers 10, 12, respectively.
However, with this SAC structure, filling the narrow gaps between the gate stacks 16 is very difficult with conventional semiconductor fabrication technologies, especially when the aspect ratio is high as is the case for state-of-the art semiconductor devices. Thus, as shown in FIG. 1, undesirable voids 18 can be formed between the gate stacks 16 during the deposition of the PMD layers 12. This has been a serious problem because adjacent contact holes can be connected through the voids 18. Thus, shorts between contact fillings (plugs) can occur unintentionally, causing device failures.
Such a problem has been recognized by the semiconductor industry, for example, as disclosed in U.S. Pat. No. 5,789,314, field on Dec. 5, 1995 and issued on Aug. 4, 1998 to Integrated Device Technology, Inc., Santa Clara. Calif. U.S. Pat. No. 5,789,314 discloses suppressing or eliminating void formation during the manufacture of integrated circuits by overlying conductive lines with an oxide layer and removing a portion of the oxide layer to create recesses at regular intervals between the conductive lines. However, such attempt has not been entirely successful as integration density increases as described above.
Accordingly, a need remains for forming gate stack structures having sidewall spacers that enable sufficient gap filling by a dielectric without forming voids therebetween.